Recently, the rapid progression of the microelectronic technology demands the devices with high speed and operates at a lower voltage to lessen the power consumption, as well as reduce the cost per unit chip. Generally, the method to approach such purpose is to scale the device dimension down. For example, for a CMOS device, as it scaling to 0.1 .mu.m and operating at 1V range, is known to have the speed enhancement of about 3X performance than the 0.35 .mu.m device operates at 3.3V. However, in short-channel MOSFETs, the stringent issues may suffer, such as hot carrier effects, punchthrough effects, parasitic resistance etc., are required to be overcome.
In addition, the parasitic capacitance--the gate fringe capacitor (C.sub.FR), around the gate electrode of a MOSFET and the junction capacitance (C.sub.J) are difficult to reduce. The lager values of the parasitic capacitance give longer RC delay time.
Hence, for realizing high speed and low-power ULSI, minimizing parasitic capacitance is demanded. The C.sub.OV, the capacitance between source/drain and the gate, and C.sub.J can be reduced by adjusting the sidewall thickness, and by self-aligned counter well doping, or by implanting a channel impurity locally around the gate electrode, as is stated in the paper, "M. Togo, et al., "A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs", Symp. On VLSI Tech. Dig., p. 38 (1996)." Besides, Togo et al. also proposed that the transistor with gate-side air-gap structure (GAS) could be used to minimize the C.sub.FR. The GAS in which a 5-nm-wide air gap formed next to the gate is found to reduce the fringe capacitance by half. Hence the gate delay time is reduced by 4.8 psec at fan out=1 and 16 psec at fan out=3 in a 0.25 .mu.m CMOS, and the power consumption is lowered compared to a conventional structure. In addition, the GAS structure does not be found to degrade electrical characteristics or reliability, as is depicted in the paper.
The fabrication of GAS structure as proposed by Togo is shown in FIGS. 1(a)-(d), and will restate as following: After gate is etching, a 20 nm wide Si.sub.3 N.sub.4 sidewall is fabricated (FIG. 1(a)). Next, a 50 nm thickness SiO.sub.2 is formed, and is followed by etching back (FIG. 1(b)). After that, the Si.sub.3 N.sub.4 sidewall is removed by a wet etching to form the air gaps (FIG. 1(c)), and 50 nm thick SiO.sub.2 layer is then deposited to form the air-gap cap and is etched back (FIG. 1(d)).